Various techniques known in the art can be used to fabricate a semiconductor device such as a transistor. In general, these techniques involve repeating, with variations, a number of characteristic steps or processes. One of these characteristic steps or processes involves applying a layer of material to an underlying substrate or to a preceding layer, and then selectively removing the material using, for example, an etch process. Another of the characteristic steps or processes involves selectively adding a dopant material to the substrate or to one or more of the subsequent layers, in order to achieve desirable electrical performance. Using these characteristic processes, a transistor, generally comprising different types of material, can be accurately formed.
Transistors may be used as memory cells in a flash memory array as well as in other applications or devices. A typical flash memory cell includes a substrate in which source and drain regions have been formed, and a gate element formed on the substrate in proximity to the source and drain regions. The gate element typically includes a floating gate and a control gate separated by an oxide-nitride-oxide (ONO) layer.
According to the conventional art, the gate element and the substrate (specifically, the source and drain regions in the substrate) are separated by a tunnel oxide layer that consists of silicon dioxide. Typically, the tunnel oxide layer is approximately 80-100 Angstroms (Å) thick. One function of the tunnel oxide is to provide a barrier for the stored electrons in the floating gate, thereby guaranteeing the reliability of the memory cell.
While conventional memory cells perform satisfactorily, it remains desirable to improve the reliability of memory cells. For instance, it is desirable to scale down the size of memory cells, so that a greater number of smaller memory cells can be put into a given area. Improvements in reliability, particularly with regard to the capacity for charge retention, become increasingly important as memory cells are scaled down in size.
Accordingly, a device and/or method providing improved memory cell performance—in particular, an improved capacity for charge retention—would be advantageous. In other words, it is desirable to scale down the sizes of memory cells while continuing to provide substantially the same reliability of larger memory cells. The present invention provides these advantages.